Field of the Invention
The present invention relates to an information processing apparatus and a method of controlling the same.
Description of the Related Art
In recent years, startup times of image forming apparatuses provided with a CPU have tended to become longer, due to the number of peripheral devices of the CPU having increased. Bus architectures for connecting such peripheral devices include PCI, for example, and the CPU initializes respective devices connected via PCI buses when starting a BIOS, a loader, or a kernel. In PCI, a plurality of nodes are arranged in a bus tree structure. That is, a PCI device and a PCI bridge are connected to a PCI bus, and the PCI bridge, in particular, is connected to another PCI bus. By interposing a PCI bridge in this manner, the PCI buses can be connected at multiple levels, enabling more PCI devices to be connected.
When initializing the PCI devices at the time of starting the BIOS, the loader, or the kernel, the CPU repeatedly searches for a bridge on the PCI bus that is closest to the CPU and searches for a bridge on a PCI bus ahead of the found bridge. Eventually, all the devices connected to the PCI buses are initialized in this manner. Note that hereinafter, PCI bridges and PCI devices are collectively referred to as PCI nodes.
Japanese Patent Laid-Open No. 2007-241526 describes a technology for achieving faster startup in such apparatuses (as described above) by connecting a system controller for searching for and initializing PCI-connected devices externally to an information processing system. In this document, the system controller, while initializing a host bus between a processor system and a bridge, initializes peripheral devices connected to the bridge. However, in this document, a PCI-PCI bridge and a host-PCI bridge are described, but description is not given regarding determination of the type of PCI bridge or execution of initialization processing.
In the case of a PCI connection, conventionally, when determining whether a PCI node connected to a PCI bus is a PCI bridge or a PCI device, the class code register of the PCI configuration register of that PCI node was referred to. That is, if the class code register is 0x06 (PCI bridge), it was determined that the PCI node was a PCI bridge.
However, in some cases, a PCI device whose class code register of the PCI configuration register is 0x06 (PCI bridge) (hereinafter, referred to as pseudo bridge) exists in an apparatus. In such cases, a further search will be conducted for a PCI node that does not exist ahead of the PCI device. At this time, for example, loss of at least one second of the startup time occurs for each pseudo bridge. In general, in an image forming apparatus aiming for a startup of no more than 30 seconds, for example, occurrence of loss of approximately one second of the startup time simply due to the BIOS can damage the value of the product as an image forming apparatus.